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adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz rev. 04 ? 2 july 2012 product data sheet 1. general description the adc0808s is a differential, high-speed , 8-bit analog-to-digital converter (adc) optimized for telecommunication transmission control systems and tape drive applications. it allows signal sampling frequencies up to 250 mhz. the adc0808s clock inputs are selectable between 1.8 v complementary metal oxide sem iconductor (cmos) or low-voltage diffe rential signals (lvds). the data output signal levels are 1.8 v cmos. all static digital inputs (clksel, ccssel , ce_n, otc, del0 and del1) are 1.8 v cmos compatible. the adc0808s offers the most flexible acquisi tion control system possible due to its programmable complete conversion signal (c cs) which allows the delay time of the acquisition clock and acquisition clock frequency to be adjusted. the adc0808s is supplied in an htqfp48 package. 2. features ? 8-bit resolution ? hig h-speed sampling rate up to 250 mhz ? ma ximum analog input frequency up to 560 mhz ? pr ogrammable acquisition output cl ock (complete conversion signal) ? dif ferential analog input ? integ rated voltage regulator or external control for analog input full-scale ? integ rated voltage regulator for input common-mode reference ? se lectable 1.8 v cmos or lvds clock input ? 1. 8 v cmos digital outputs ? 1. 8 v cmos compatible static digital inputs ? bina ry or 2?s complement cmos outputs ? only 2 clock cycles latency ? ind ustrial temperature range from ? 40 ? c to +85 ? c ? htqf p48 package 3. applications ? 2.5g and 3g cellular base infrastructure radio transceivers ? wireless ac cess systems ? fixed t elecommunications
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 2 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz ? optical networking ? wir eless local area networ k (wlan) infrastructure ? t ape drive applications 4. ordering information table 1. ordering information type number sampling frequency (mhz) package name description version ADC0808S125HW-C1 125 htqfp48 plastic thermal enhanced thin quad flat package; 48 leads; body 7 ? 7 ? 1 mm; exposed die pad sot545-2 adc0808s250hw-c1 250 5. block diagram 8 8 001aai267 track and hold adc core latch latch resistor ladders clock driver outputs enable cmadc reference internal reference adc0808s u/i inn in del0 del1 ccs 17 39 38 19 29 33 32 30 fsin/ refsel 37 36 40 26 21 20 ccssel d0 to d7 otc ir cmadc clksel clk+ clk? ce_n latch fig 1. block diagram
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 3 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 6. pinning information 6.1 pinning adc0808s ognd1 clksel d3 i.c. i.c. v cca1(3v3) v cco1(1v8) in d4 inn i.c. agnd2 ognd2 fsin/refsel d5 cmadc i.c. agnd1 dgnd v cco2(1v8) nc1v8 d6 ccssel i.c. n.c. v cco3(1v8) i.c. d7 d2 i.c. ognd4 ognd3 i.c. ccs d1 i.c. v cco4(1v8) ce_n i.c. ir d0 otc del1 dgnd1 del0 v ccd1(1v8) n.c. clk? clk+ 001aai268 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 fig 2. pin configuration 6.2 pin description table 2. pin description symbol pin type [1] description ognd1 1 g data output ground 1 d3 2 o data output bit 3 i.c. 3 - internally connected; leave open v cco1(1v8) 4 p data output supply voltage 1 (1.8 v) d4 5 o data output bit 4 i.c. 6 - internally connected; leave open ognd2 7 g data output ground 2 d5 8 o data output bit 5 i.c. 9 - internally connected; leave open v cco2(1v8) 10 p data output supply voltage 2 (1.8 v) d6 11 o data output bit 6 i.c. 12 - internally connected; leave open v cco3(1v8) 13 p data output supply voltage 3 (1.8 v) d7 14 o data output bit 7
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 4 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz [1] see table 3. i.c. 15 - internally connected; leave open ognd3 16 g data output ground 3 ccs 17 o complete conversion signal output i.c. 18 - internally connected; leave open ce_n 19 i(cmos) chip enable input (active low) ir 20 o(cmos) in-range output otc 21 i(cmos) control input for 2?s complement output dgnd1 22 g digital ground 1 v ccd1(1v8) 23 p digital supply voltage 1 (1.8 v) n.c. 24 - not connected n.c. 25 - not connected ccssel 26 i(cmos) control input for ccs frequency selection nc1v8 27 i not connected or connected to v ccd1(1v8) agnd1 28 g analog ground 1 cmadc 29 o regulator common-mode adc output fsin/refsel 30 i full-scale reference voltage input/internal or external reference selection agnd2 31 g analog ground 2 inn 32 i complementary analog input in 33 i analog input v cca1(3v3) 34 p analog supply voltage 1 (3.3 v) i.c. 35 - internally connected; leave open clksel 36 i(cmos) control input for clock input selection clk+ 37 i clock input clk 38 i complementary clock input del0 39 i(cmos) complete conversion signal delay input 0 del1 40 i(cmos) complete conversion signal delay input 1 d0 41 o data output bit 0 i.c. 42 - internally connected; leave open v cco4(1v8) 43 p data output supply voltage 4 (1.8 v) d1 44 o data output bit 1 i.c. 45 - internally connected; leave open ognd4 46 g data output ground 4 d2 47 o data output bit 2 i.c. 48 - internally connected; leave open dgnd - g digital ground; exposed die pad table 2. pin description ?continued symbol pin type [1] description
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 5 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz table 3. pin type description type description i input o output i(cmos) 1.8 v cmos level input o(cmos) 1.8 v cmos level output p power supply g ground 7. functional description 7.1 cmos/lvds clock input the circuit has two clock inputs clk+ and clk ? , with two modes of operation: ? lvds mode: clk+ and clk ? inputs are at differential lvds levels. an external resistor of between 80 ? and 120 ? is required; see figure 3. 001aah720 lvds driver receiver v gpd v o(dif) undefined state minimum v idth maximum v idth clk+ clk? fig 3. lvds clock input ? 1.8 v cmos mode: clk+ input is at 1.8 v cmos level and samplin g is done on the rising edge of the clock input signal. in this case pin clk ? must be grounded; see figure 4. 001aai272 cmos driver clk? clk+ fig 4. cmos clock input
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 6 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz table 4. clock input format selection pin clksel clock input signal pins clk+ and clk ? high or not connected lvds low 1.8 v cmos 7.2 digital output coding the digital outputs are 1.8 v cmos compatible. the data output format can be ei ther binary or 2?s complement. table 5. output coding with differential inputs v i(p-p) = 2.0 v; v ref(fs) = 1.25 v; typical values to agnd. code inputs (v) output outputs d7 to d0 v i(in) v i(inn) pin ir binary 2?s complement underflow < 0.45 > 1.45 low 0000 0000 1000 0000 0 0.45 1.45 high 0000 0000 1000 0000 1 - - high 0000 0001 1000 0001 : : : : : : 127 0.95 0.95 high 0111 1111 1111 1111 : : : : : : 254 - - high 1111 1110 0111 1110 255 1.45 0.45 high 1111 1111 0111 1111 overflow > 1.45 < 0.45 low 1111 1111 0111 1111 the in-range cmos output pin ir will be hi gh during normal oper ation. when the adc input reaches either positive or negati ve full-scale, the ir output will be low. selection between output coding is controlled by pins otc and ce_n. table 6. output format selection 2?s complement outputs chip enable output data pin otc pin ce_n pins d0 to d7, ccs and ir low low active; binary high low active; 2?s complement x [1] high high-impedance [1] x = don?t care.
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 7 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 7.3 timing output in, inn clk+, clk? n d0 to d7 50 % data n ? 2n ? 1 data data data n + 1 n t d(o) t d(s) t h(o) 001aab892 sample n sample n + 1 sample n + 2 sample n + 3 sample n + 4 fig 5. output timing diag ram (ccs not selected) 7.4 timing complete conversion signal the adc0808s generates an adjustable clock output signal on pin ccs called complete conversion signal, which can be used to control the acquisition of converted output data to the digital circuit connected to the adc0808s output data bus. two logic input pins del0 and del1 control the d elay of the edge of the ccs signal to achieve an optimal position in the stable, usable zone of the data as shown in figure 6. table 7. complete conver sion signal selection pin del0 pin del1 pin ccs low low high-impedance high low active; see table 13 low high high high pin ccssel selects the ccs frequency; see table 8. table 8. complete conversion signal frequency selection pin ccssel ccs frequency (f ccs ) high or not connected f clk low f clk / 2
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 8 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 001aab893 ccs (f clk ) ccs (f clk / 2) d0 to d7 50 % 50 % data n ? 2n ? 1 data data data n + 1 n t d(ccs) fig 6. complete conversion si gnal timing diagram using ccs 7.5 full-scale input selection the adc0808s has an internal reference circuit which can be overruled by an external reference voltage. this can be done with the full-scale reference voltage (v ref(fs) ) according to table 9. the adc provides the required common-mode volt a ge on pin cmadc. in case of internal regulation, the regulator output voltage on pin cmadc is 0.95 v. table 9. full-scale input selection full-scale reference voltage v ref(fs) common-mode output voltage v o(cm) maximum peak-to-peak input voltage v i(p-p)(max) 1.15 v 0.8 v 1.825 v 1.20 v 0.86 v 1.91 v 1.25 v 0.94 v 1.99 v 1.30 v 1.01 v 2.08 v 1.35 v 1.09 v 2.16 v the internal reference circuit is enabled by connecting pin fsin to ground. the common-mode output voltage v o(cm) on pin cmadc will then be 0.95 v, and the ma ximum peak-to-peak input voltage v i(p-p)(max) will be 2.0 v; see figure 7 and figure 8. the adc full-scale input selectio n pr inciple is shown in figure 9.
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 9 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz v fsin (v) 0 1.4 1.3 1.2 1.1 001aai270 0.9 0.8 1.0 1.1 v o(cm) (v) 0.7 fig 7. adc common-mode output voltage v o(cm) as a function of v fsin v fsin (v) 1.0 1.4 1.3 1.2 1.1 001aai269 2.0 1.9 2.1 2.2 v i(p-p)(max) (v) 1.8 fig 8. adc maximum peak-to -peak input voltage v i(p-p)(max) as a function of v fsin a. external reference voltage applied b. internal reference circuit enabled fig 9. adc full-scale input selection
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 10 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 8. limiting values table 10. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage ? 0.5 +4.6 v v ccd digital supply voltage ? 0.5 +2.5 v v cco output supply voltage ? 0.5 +2.5 v v i(in) input voltage on pin in referenced to agnd ? 0.5 v cca + 1 v v i(inn) input voltage on pin inn referenced to agnd ? 0.5 v cca + 1 v v i(clk) input voltage on pin clk referenced to dgnd ? 0.5 v ccd + 0.55 v t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 150 ?c 9. thermal characteristics table 11. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 36.2 k/w r th(j-c) thermal resistance from junction to case [1] 14.3 k/w [1] in compliance with jedec test board, in free air. 10. static characteristics table 12. static characteristics v cca = 3.0 v to 3.6 v; v ccd = 1.65 v to 1.95 v; v cco = 1.65 v to 1.95 v; pins agnd1, agnd2 and dgnd1 shorted together; t amb = ? ? ? ? ? ? symbol parameter conditions min typ max unit supplies v cca analog supply voltage 3.0 3.3 3.6 v v ccd digital supply voltage 1.65 1.80 1.95 v v cco output supply voltage 1.65 1.80 1.95 v i cca analog supply current f clk = 125 mhz; f i = 1.25 mhz - 60 - ma i ccd digital supply current f clk = 125 mhz; f i = 1.25 mhz - 12 - ma i cco output supply current f clk = 125 mhz; f i = 1.25 mhz - 11 - ma p tot total power dissipation f clk = 125 mhz; f i = 1.25 mhz - 240 - mw clock inputs: pins clk+ and clk ? r i input resistance [1] - 10 - k? c i input capacitance [1] - 1 - pf lvds clock input; see figure 3 ? v i input voltage range v i on pin clk+ or clk ? ; |v gpd | < 50 mv [2] 825 - 1 575 mv
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 11 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz [1] guaranteed by design. [2] _ v gpd _ is the voltage of ground potential difference across or between boards. [3] the adc input range can be adjusted with an external refer ence voltage applied to pin fsin. this voltage must be referenced to agnd. v idth input differential threshold voltage |v gpd | < 50 mv [2] 100 - +100 mv i i input current 825 mv < v i < 1 575 mv - - 50 p a 1.8 v cmos clock input; see figure 4 v il low-level input voltage dgnd - 0.2v ccd v v ih high-level input voltage 0.8v ccd - v ccd v i il low-level input current v il = 0.2v ccd - - 50 p a i ih high-level input current v ih = 0.8v ccd - - 50 p a analog inputs: pins in and inn r i input resistance [1] - 1.0 - m : c i input capacitance [1] - 1.0 - pf v i(cm) common-mode input voltage v i(in) = v i(inn) ; output code = 127 0.7 0.95 1.0 v digital input pins: otc, ce_n, del0, del1, clksel and ccssel v il low-level input voltage dgnd - 0.2v ccd v v ih high-level input voltage 0.8v ccd - v ccd v i il low-level input current v il = 0.3v ccd - - 50 p a i ih high-level input current v ih = 0.7v ccd - - 50 p a voltage controlled regulator output: pin cmadc v o(cm) common-mode output voltage 0.85 0.95 1.1 v reference voltage input: pin fsin [3] v fsin voltage on pin fsin internal reference - 0 0.6 v external reference 1.15 1.25 1.35 v i i(fsin) input current on pin fsin - 12 - p a v i(p-p)(max) maximum peak-to-peak input voltage internal reference 1.92 2 2.03 v external reference v fsin = 1.15 v 1.80 1.825 1.85 v v fsin = 1.25 v 1.98 1.99 2.03 v v fsin = 1.35 v 2.11 2.16 2.18 v digital outputs: pins d0 to d7, ccs and ir v ol low-level output voltage ognd - 0.2 v v oh high-level output voltage v cco 0.2 - v cco v table 12. static characteristics ?continued v cca = 3.0 v to 3.6 v; v ccd = 1.65 v to 1.95 v; v cco = 1.65 v to 1.95 v; pins agnd1, agnd2 and dgnd1 shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 2.0 v 0.5 db; v i(cm) = 0.95 v; v fsin = 0 v; typical values are measured at v cca = 3.3 v, v ccd = v cco = 1.8 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 12 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 11. dynamic characteristics table 13. dynamic characteristics v cca = 3.0 v to 3.6 v; v ccd = 1.65 v to 1.95 v; v cco = 1.65 v to 1.95 v; pins agnd1, agnd2 and dgnd1 shorted together; t amb = 40 q c to +85 q c; v i(in) v i(inn) = 2.0 v 0.5 db; v i(cm) = 0.95 v; v fsin = 0 v; typical values are measured at v cca = 3.3 v, v ccd = v cco = 1.8 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit clock timing input: pins clk+ and clk f clk(min) minimum clock frequency - - 1 mhz f clk(max) maximum clock frequency 250 - - mhz t w(clk) clock pulse width f clk = 125 mhz 1.8 - - ns timing output: pins d0 to d7 and ir [1] ; see figure 5 t d(s) sampling delay time 1.8 v cmos clock - 1.3 - ns lvds clock - 1.65 - ns t h(o) output hold time 1.8 v cmos clock 3.3 4.4 - ns lvds clock 4.2 4.8 - ns t d(o) output delay time 1.8 v cmos clock - 5.4 6.9 ns lvds clock - 5.8 7.3 ns timing complete conversion signal: pin ccs; see figure 6 f ccs(max) maximum ccs frequency 125 - - mhz t d(ccs) ccs delay time del0 = high; del1 = low - 0.3 - ns del0 = low; del1 = high - 0.8 - ns del0 = high; del1 = high - 1.9 - ns 3-state output delay time: pins ccs, ir and d7 to d0 t dzh float to active high delay time - 2.1 - ns t dzl float to active low delay time - 2.2 - ns t dhz active high to float delay time - 3.3 - ns t dlz active low to float delay time - 2.9 - ns analog signal processing (50 % clock duty factor); see section 12 inl integral non-linearity f clk = 20 mhz; f i = 21.4 mhz - r 0.82 - lsb dnl differential non-linearity f clk = 20 mhz; f i = 21.4 mhz; no missing code guaranteed - r 0.4 - lsb e o offset error v cca = 3.3 v; v ccd = 1.8 v; t amb = 25 q c; output code = 127 - 2.5 - mv e g gain error spread from device to device; v cca = 3.3 v; v ccd = 1.8 v; t amb = 25 q c - 1.85 - % b bandwidth f clk = 125 mhz; 3 db; full-scale input [2] - 560 - mhz thd total harmonic distortion f clk = 125 mhz; f i = 78 mhz [3] - 53 - db f clk = 250 mhz; f i = 125 mhz - 53 - db n th(rms) rms thermal noise shorted input; f clk = 125 mhz - 0.5 - lsb s/n signal-to-noise ratio f clk = 125 mhz; f i = 78 mhz [4] - 48 - dbc f clk = 250 mhz; f i = 125 mhz - 47 - dbc
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 13 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz [1] output data acquisition: the output data is available after the maximum delay of t d(o) . [2] the ?3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input be ing a full-scale sine wave. [3] the total harmonic distortion is obtained with the addition of the first five harmonics. [4] the signal-to-noise ratio takes in to account all har monics above five and noise up to nyquist frequency. [5] intermodulation measured relative to either tone with analog input frequencies f 1 and f 2 . the two input signals have the same amplitude and the total amplitude of both signals prov ides full-scale to the converter ( ?6 db below full-scale for each input signal). imd3 is the ratio of the rms value of either input tone to the rms val ue of the worst case third-order intermodulation product. 12. definitions 12.1 static parameters 12.1.1 integral non-linearity integral non-linearity (inl) is defined as t he deviation of the transfer function from a best-fit straight line (linear regression comput ation). the inl of the code is obtained from the equation: inl i ?? v in i ?? v in ideal ?? ? s ---------------------------------------------- - = (1) where: s corresponds to the slope of the ideal straight line (code width), i corresponds to th e code value, v in is the input voltage. 12.1.2 differential non-linearity differential non-linearity (dnl ) is the deviation in code width from the value of 1 lsb. dnl i ?? v in i1 + ?? v in i ?? ? s -------------------------------------------- = (2) where: v in is the input voltage; i is a code value from 0 to (2 n ? 2). 12.2 dynamic parameters figure 10 shows the spectrum of a single tone fu ll-scale input s ine wa ve of frequency f t , conforming to coherent sampling and which is digitized by the adc under test. coherent sampling: (f t / f s = m / n, where m = number of cycles and n = number of samples, m and n values being relatively prime). sfdr spurious free dynamic range f clk = 125 mhz; f i = 78 mhz - 55 - dbc f clk = 250 mhz; f i = 125 mhz - 55 - dbc imd2 second-order intermodulation d istortion f 1 = 124 mhz; f 2 = 126 mhz; f clk = 250 mhz [5] - ? 55 - db imd3 third-order intermodulation d istortion f 1 = 124 mhz; f 2 = 126 mhz; f clk = 250 mhz [5] - ? 60 - db table 13. dynamic characteristics ?continued v cca = 3.0 v to 3.6 v; v ccd = 1.65 v to 1.95 v; v cco = 1.65 v to 1.95 v; pins agnd1, agnd2 and dgnd1 shorted together; t amb = ? ? ? ? ? ? symbol parameter conditions min typ max unit
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 14 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz a 2 a 1 magnitude frequency 001aag627 sfdr a k s a 3 a = harmonic. s = single tone. fig 10. single tone spectrum of full-s cale input sine wave of frequency f t remark: p noise in the equations in the following se ctions, is the sum of noise sources which include random noise, non-linearities, sampling time errors, and quantization noise. 12.2.1 signal-to-noise and distortion (sinad) sinad is the ratio of the output signal power to the noise plus distortion power for a given sample rate and input frequency, excluding the dc component: sinad db ?? 10log 10 p signal p noise distortion + --------------------------------------- - ?? ?? = (3) 12.2.2 effective number of bits (enob) enob is derived from sinad and gives the theoretical resolution required by an ideal adc to obtain the same sinad measured on the real adc. a good approximation gives: enob sinad 1.76 ? 6.02 ---------------------------------- = (4) 12.2.3 total harmonic distortion (thd) thd is the ratio of the power of the harmoni cs to the power of the fundamental. for k ? 1 h armonics the thd is: thd db ?? 10log 10 p harmonics p signal ------------------------- ?? ?? = (5) where:
p harmonics a 2 2 a 3 2 ? a k 2 +++ = p signal a 1 2 = adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 15 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz (6) (7) the value of k is usually 6 (thd is calculated based on the first 5 harmonics). 12.2.4 signal-to-noise ratio (s/n) s/n is the ratio of the output signal power to the noise power, excluding the harmonics and the dc component: sn ? 10log 10 p signal p noise ---------------- ?? ?? = (8) 12.2.5 spurious free dynamic range (sfdr) the sfdr value specifies the available signal range as the spectral distance between the amplitude of the fundamental (a 1 ) and the amplitude of the largest spurious harmonic and non-harmonic (max (s)), excluding the dc component: sfdr db ?? 20log 10 a 1 max s ?? ----------------- - ?? ?? = (9) 12.2.6 intermodulation distortion (imd) f 1 ? f 2 2f 2 ? f 1 2f 1 ? f 2 f 1 + f 2 2f 2 2f 1 f 2 f 1 f 1 + 2f 2 3f 2 2f 1 + f 2 3f 1 magnitude frequency 001aag628 fig 11. spectrum of dual tone input sine wave of frequencies f 1 and f 2 the second-order and third-order intermodulation distortion products imd2 and imd3 are defined using a dual tone input sinusoid, where f 1 and f 2 are chosen according to the coherence criterion. imd is the ratio of the rms value of either to ne to the rms value of the worst, second or third-order intermodulation products.
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 16 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz the total intermodulation distortion is given by: imd db ?? 10log 10 p intermod p signal ---------------------- ?? ?? = (10) where: p intermod a im f 1 f 2 ? ?? 2 a im f 1 f 2 + ?? 2 ? a im f 1 2f 2 ? ?? 2 a im f 1 2f 2 + ?? 2 ? +++ = ? a + im 2f 1 f 2 ? ?? 2 a im 2f 1 f 2 + ?? 2 + (11) where a im f n ?? 2 is the power in the intermodulation component at f n . p signal a f 1 2 a f 2 2 += (12)
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 17 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 13. package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) ce ly wv references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 7.1 6.9 0.5 9.1 8.9 0.9 0.6 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot545-2 ms-026 03-04-07 04-01-29 d (1) e (1) 7.1 6.9 9.1 8.9 d h e h 4.6 4.4 4.6 4.4 0.9 0.6 b p e e a 1 a l p detail x l b 12 1 48 37 d h b p e h a 2 v m b d z d a c z e e v m a x 25 36 24 13 y pin 1 index w m w m 0 2.5 5 mm scale htqfp48: plastic thermal enhanced thin quad flat package; 48 leads; body 7 x 7 x 1 mm; exposed die pad sot545-2 d h e h exposed die pad side (a ) 3 fig 12. package outline sot545-2 (htqfp48)
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 18 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 19 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 13) than a snpb process, thus r educing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 14 and 15 table 14. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 15. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2 000 > 2 000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow sold ering, see figure 13.
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 20 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature msl: moisture sensitivity level fig 13. temperature profiles for large and small components for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? .
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 21 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 15. revision history table 16. revision history document id release date data sheet status change notice supersedes adc0808s125_adc0808s250_4 20120702 product data sheet - adc0808s125_a d c0808s250_3 adc0808s125_adc0808s250_3 20090224 product data sheet - adc0808s125_a d c0808s250_2 modifications: table ? 13 updated. adc0808s125_adc0808s250_2 20081007 product data sheet - tda9917_1 tda9917_1 20060609 objective data sheet - - 16. contact information for more information or sales office addresses, please visit: http://www.idt.com
adc0808s125_adc0808s250_4 ? idt 2012. all rights reserved. product data sheet rev. 04 ? 2 july 2012 22 of 22 integrated device technology adc0808s125/250 single 8-bit adc, up to 125 mhz or 250 mhz 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 cmos/lvds clock input. . . . . . . . . . . . . . . . . . 5 7.2 digital output coding . . . . . . . . . . . . . . . . . . . . . 6 7.3 timing output . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.4 timing complete conversion signal. . . . . . . . . . 7 7.5 full-scale input selection . . . . . . . . . . . . . . . . . 8 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 9 thermal characteristics . . . . . . . . . . . . . . . . . 10 10 static characteristics. . . . . . . . . . . . . . . . . . . . 10 11 dynamic characteristics . . . . . . . . . . . . . . . . . 12 12 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 13 12.1.1 integral non-linearity . . . . . . . . . . . . . . . . . . . 13 12.1.2 differential non-linearity . . . . . . . . . . . . . . . . . 13 12.2 dynamic parameters . . . . . . . . . . . . . . . . . . . 13 12.2.1 signal-to-noise and distortion (sinad) . . . . 14 12.2.2 effective number of bits (enob) . . . . . . . . . 14 12.2.3 total harmonic distortion (thd) . . . . . . . . . . 14 12.2.4 signal-to-noise ratio (s/n) . . . . . . . . . . . . . . . 15 12.2.5 spurious free dynamic range (sfdr). . . . . 15 12.2.6 intermodulation distortion (imd) . . . . . . . . . . 15 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 17 14 soldering of smd packages . . . . . . . . . . . . . . 18 14.1 introduction to soldering. . . . . . . . . . . . . . . . . 18 14.2 wave and reflow soldering. . . . . . . . . . . . . . . 18 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 18 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 19 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 21 16 contact information . . . . . . . . . . . . . . . . . . . . 21 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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